<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>DIT</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">DIT, Data Independent Timing</h1><p>The DIT characteristics are:</p><h2>Purpose</h2>
        <p>Allows access to the Data Independent Timing bit.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_DIT is implemented. Otherwise, direct accesses to DIT are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>DIT is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_25">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="7"><a href="#fieldset_0-63_25">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-24_24">DIT</a></td><td class="lr" colspan="24"><a href="#fieldset_0-23_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-63_25">Bits [63:25]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-24_24">DIT, bit [24]</h4><div class="field">
      <p>Data Independent Timing.</p>
    <table class="valuetable"><tr><th>DIT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The architecture makes no statement about the timing properties of any instructions.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>The architecture requires that:</p>
<ul>
<li>
<p>The timing of every load and store instruction is insensitive to the value of the data being loaded or stored.</p>

</li><li>
<p>For certain data processing instructions, the instruction takes a time which is independent of:</p>
<ul>
<li>
<p>The values of the data supplied in any of its registers.</p>

</li><li>
<p>The values of the NZCV flags.</p>

</li></ul>

</li><li>
<p>For certain data processing instructions, the response of the instruction to asynchronous exceptions does not vary based on:</p>
<ul>
<li>
<p>The values of the data supplied in any of its registers.</p>

</li><li>
<p>The values of the NZCV flags.</p>

</li></ul>

</li></ul></td></tr></table><p>The data processing instructions affected by this bit are:</p>
<ul>
<li>
<p>All cryptographic instructions. These instructions are:</p>
<ul>
<li><span class="instruction">AESD</span>, <span class="instruction">AESE</span>, <span class="instruction">AESIMC</span>, <span class="instruction">AESMC</span>, <span class="instruction">SHA1C</span>, <span class="instruction">SHA1H</span>, <span class="instruction">SHA1M</span>, <span class="instruction">SHA1P</span>, <span class="instruction">SHA1SU0</span>, <span class="instruction">SHA1SU1</span>, <span class="instruction">SHA256H</span>, <span class="instruction">SHA256H2</span>, <span class="instruction">SHA256SU0</span>, <span class="instruction">SHA256SU1</span>, <span class="instruction">SHA512H</span>, <span class="instruction">SHA512H2</span>, <span class="instruction">SHA512SU0</span>, <span class="instruction">SHA512SU1</span>, <span class="instruction">EOR3</span>, <span class="instruction">RAX1</span>, <span class="instruction">XAR</span>, <span class="instruction">BCAX</span>, <span class="instruction">SM3SS1</span>, <span class="instruction">SM3TT1A</span>, <span class="instruction">SM3TT1B</span>, <span class="instruction">SM3TT2A</span>, <span class="instruction">SM3TT2B</span>, <span class="instruction">SM3PARTW1</span>, <span class="instruction">SM3PARTW2</span>, <span class="instruction">SM4E</span>, and <span class="instruction">SM4EKEY</span>.
</li></ul>

</li><li>
<p>A subset of those instructions which use the general-purpose register file. These instructions are:</p>
<ul>
<li>
<p><span class="instruction">ADC</span>, <span class="instruction">ADCS</span>, <span class="instruction">ADD</span>, <span class="instruction">ADDS</span>, <span class="instruction">AND</span>, <span class="instruction">ANDS</span>, <span class="instruction">ASR</span>, <span class="instruction">ASRV</span>, <span class="instruction">BFC</span>, <span class="instruction">BFI</span>, <span class="instruction">BFM</span>, <span class="instruction">BFXIL</span>, <span class="instruction">BIC</span>, <span class="instruction">BICS</span>, <span class="instruction">CCMN</span>, <span class="instruction">CCMP</span>, <span class="instruction">CFINV</span>, <span class="instruction">CINC</span>, <span class="instruction">CINV</span>, <span class="instruction">CLS</span>, <span class="instruction">CLZ</span>, <span class="instruction">CMN</span>, <span class="instruction">CMP</span>, <span class="instruction">CNEG</span>, <span class="instruction">CSEL</span>, <span class="instruction">CSET</span>, <span class="instruction">CSETM</span>, <span class="instruction">CSINC</span>, <span class="instruction">CSINV</span>, <span class="instruction">CSNEG</span>, <span class="instruction">EON</span>, <span class="instruction">EOR</span>, <span class="instruction">EXTR</span>, <span class="instruction">LSL</span>, <span class="instruction">LSLV</span>, <span class="instruction">LSR</span>, <span class="instruction">LSRV</span>, <span class="instruction">MADD</span>, <span class="instruction">MNEG</span>, <span class="instruction">MOV</span>, <span class="instruction">MOVK</span>, <span class="instruction">MOVN</span>, <span class="instruction">MOVZ</span>, <span class="instruction">MSUB</span>, <span class="instruction">MUL</span>, <span class="instruction">MVN</span>, <span class="instruction">NEG</span>, <span class="instruction">NEGS</span>, <span class="instruction">NGC</span>, <span class="instruction">NGCS</span>, <span class="instruction">NOP</span>, <span class="instruction">ORN</span>, <span class="instruction">ORR</span>, <span class="instruction">RBIT</span>, <span class="instruction">REV</span>, <span class="instruction">REV16</span>, <span class="instruction">REV32</span>, <span class="instruction">REV64</span>, <span class="instruction">RMIF</span>, <span class="instruction">ROR</span>, <span class="instruction">RORV</span>, <span class="instruction">SBC</span>, <span class="instruction">SBCS</span>, <span class="instruction">SBFIZ</span>, <span class="instruction">SBFM</span>, <span class="instruction">SBFX</span>, <span class="instruction">SETF8</span>, <span class="instruction">SETF16</span>, <span class="instruction">SMADDL</span>, <span class="instruction">SMNEGL</span>, <span class="instruction">SMSUBL</span>, <span class="instruction">SMULH</span>, <span class="instruction">SMULL</span>, <span class="instruction">SUB</span>, <span class="instruction">SUBS</span>, <span class="instruction">SXTB</span>, <span class="instruction">SXTH</span>, <span class="instruction">SXTW</span>, <span class="instruction">TST</span>, <span class="instruction">UBFIZ</span>, <span class="instruction">UBFM</span>, <span class="instruction">UBFX</span>, <span class="instruction">UMADDL</span>, <span class="instruction">UMNEGL</span>, <span class="instruction">UMSUBL</span>, <span class="instruction">UMULH</span>, <span class="instruction">UMULL</span>, <span class="instruction">UXTB</span>, and <span class="instruction">UXTH</span>.</p>

</li><li>
<p>If FEAT_CRC32 is implemented, <span class="instruction">CRC32B</span>, <span class="instruction">CRC32H</span>, <span class="instruction">CRC32W</span>, <span class="instruction">CRC32X</span>, <span class="instruction">CRC32CB</span>, <span class="instruction">CRC32CH</span>, <span class="instruction">CRC32CW</span>, and <span class="instruction">CRC32CX</span>.</p>

</li></ul>

</li><li>
<p>A subset of those instructions which use the SIMD&amp;FP register file. These instructions are:</p>
<ul>
<li><span class="instruction">ABS</span>, <span class="instruction">ADD</span>, <span class="instruction">ADDHN</span>, <span class="instruction">ADDHN2</span>, <span class="instruction">ADDP</span>, <span class="instruction">ADDV</span>, <span class="instruction">AND</span>, <span class="instruction">BIC</span>, <span class="instruction">BIF</span>, <span class="instruction">BIT</span>, <span class="instruction">BSL</span>, <span class="instruction">CLS</span>, <span class="instruction">CLZ</span>, <span class="instruction">CMEQ</span>, <span class="instruction">CMGE</span>, <span class="instruction">CMGT</span>, <span class="instruction">CMHI</span>, <span class="instruction">CMHS</span>, <span class="instruction">CMLE</span>, <span class="instruction">CMLT</span>, <span class="instruction">CMTST</span>, <span class="instruction">CNT</span>, <span class="instruction">DUP</span>, <span class="instruction">EOR</span>, <span class="instruction">EXT</span>, <span class="instruction">FCSEL</span>, <span class="instruction">INS</span>, <span class="instruction">MLA</span>, <span class="instruction">MLS</span>, <span class="instruction">MOV</span>, <span class="instruction">MOVI</span>, <span class="instruction">MUL</span>, <span class="instruction">MVN</span>, <span class="instruction">MVNI</span>, <span class="instruction">NEG</span>, <span class="instruction">NOT</span>, <span class="instruction">ORN</span>, <span class="instruction">ORR</span>, <span class="instruction">PMUL</span>, <span class="instruction">PMULL</span>, <span class="instruction">PMULL2</span>, <span class="instruction">RADDHN</span>, <span class="instruction">RADDHN2</span>, <span class="instruction">RBIT</span>, <span class="instruction">REV16</span>, <span class="instruction">REV32</span>, <span class="instruction">RSHRN</span>, <span class="instruction">RSHRN2</span>, <span class="instruction">RSUBHN</span>, <span class="instruction">RSUBHN2</span>, <span class="instruction">SABA</span>, <span class="instruction">SABD</span>, <span class="instruction">SABAL</span>, <span class="instruction">SABAL2</span>, <span class="instruction">SABDL</span>, <span class="instruction">SABDL2</span>, <span class="instruction">SADALP</span>, <span class="instruction">SADDL</span>, <span class="instruction">SADDL2</span>, <span class="instruction">SADDLP</span>, <span class="instruction">SADDLV</span>, <span class="instruction">SADDW</span>, <span class="instruction">SADDW2</span>, <span class="instruction">SHADD</span>, <span class="instruction">SHL</span>, <span class="instruction">SHLL</span>, <span class="instruction">SHLL2</span>, <span class="instruction">SHRN</span>, <span class="instruction">SHRN2</span>, <span class="instruction">SHSUB</span>, <span class="instruction">SLI</span>, <span class="instruction">SMAX</span>, <span class="instruction">SMAXP</span>, <span class="instruction">SMAXV</span>, <span class="instruction">SMIN</span>, <span class="instruction">SMINP</span>, <span class="instruction">SMINV</span>, <span class="instruction">SMLAL</span>, <span class="instruction">SMLAL2</span>, <span class="instruction">SMLSL</span>, <span class="instruction">SMLSL2</span>, <span class="instruction">SMOV</span>, <span class="instruction">SMULL</span>, <span class="instruction">SMULL2</span>, <span class="instruction">SQDMULH</span> (by element), <span class="instruction">SQDMULH</span> (vector), <span class="instruction">SQRDMLAH</span> (by element), <span class="instruction">SQRDMLAH</span> (vector), <span class="instruction">SQRDMULH</span> (by element), <span class="instruction">SQRDMULH</span> (vector), <span class="instruction">SRI</span>, <span class="instruction">SSHL</span>, <span class="instruction">SSHLL</span>, <span class="instruction">SSHLL2</span>, <span class="instruction">SSHR</span>, <span class="instruction">SSRA</span>, <span class="instruction">SSUBL</span>, <span class="instruction">SSUBL2</span>, <span class="instruction">SSUBW</span>, <span class="instruction">SSUBW2</span>, <span class="instruction">SUB</span>, <span class="instruction">SUBHN</span>, <span class="instruction">SUBHN2</span>, <span class="instruction">SXTL</span>, <span class="instruction">SXTL2</span>, <span class="instruction">TBL</span>, <span class="instruction">TBX</span>, <span class="instruction">TRN1</span>, <span class="instruction">TRN2</span>, <span class="instruction">UABA</span>, <span class="instruction">UABAL</span>, <span class="instruction">UABAL2</span>, <span class="instruction">UABD</span>, <span class="instruction">UABDL</span>, <span class="instruction">UABDL2</span>, <span class="instruction">UADALP</span>, <span class="instruction">UADDL</span>, <span class="instruction">UADDL2</span>, <span class="instruction">UADDLP</span>, <span class="instruction">UADDLV</span>, <span class="instruction">UADDW</span>, <span class="instruction">UADDW2</span>, <span class="instruction">UHADD</span>, <span class="instruction">UHSUB</span>, <span class="instruction">UMAX</span>, <span class="instruction">UMAXP</span>, <span class="instruction">UMAXV</span>, <span class="instruction">UMIN</span>, <span class="instruction">UMINP</span>, <span class="instruction">UMINV</span>, <span class="instruction">UMLAL</span>, <span class="instruction">UMLAL2</span>, <span class="instruction">UMLSL</span>, <span class="instruction">UMOV</span>, <span class="instruction">UMLSL2</span>, <span class="instruction">UMULL</span>, <span class="instruction">UMULL2</span>, <span class="instruction">USHL</span>, <span class="instruction">USHLL</span>, <span class="instruction">USHLL2</span>, <span class="instruction">USHR</span>, <span class="instruction">USRA</span>, <span class="instruction">USUBL</span>, <span class="instruction">USUBL2</span>, <span class="instruction">USUBW</span>, <span class="instruction">USUBW2</span>, <span class="instruction">UXTL</span>, <span class="instruction">UXTL2</span>, <span class="instruction">UZP1</span>, <span class="instruction">UZP2</span>, <span class="instruction">XTN</span>, <span class="instruction">XTN2</span>, <span class="instruction">ZIP1</span>, and <span class="instruction">ZIP2</span>.
</li></ul>

</li></ul>
<div class="note"><span class="note-header">Note</span><p>The architecture makes no statement about the timing properties when the PSTATE.DIT bit is not set. However, it is likely that many of these instructions have timing that is invariant of the data in many situations.</p><p>In particular, Arm strongly recommends that the Armv8.3 pointer authentication instructions do not have their timing dependent on the key value used in the pointer authentication in all cases, regardless of the PSTATE.DIT bit.</p></div><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-23_0">Bits [23:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing DIT</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, DIT</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b011</td><td>0b0100</td><td>0b0010</td><td>0b101</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24);
elsif PSTATE.EL == EL1 then
    X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24);
elsif PSTATE.EL == EL2 then
    X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24);
elsif PSTATE.EL == EL3 then
    X[t, 64] = Zeros(39):PSTATE.DIT:Zeros(24);
                </p><h4 class="assembler">MSR DIT, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b011</td><td>0b0100</td><td>0b0010</td><td>0b101</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    PSTATE.DIT = X[t, 64]&lt;24&gt;;
elsif PSTATE.EL == EL1 then
    PSTATE.DIT = X[t, 64]&lt;24&gt;;
elsif PSTATE.EL == EL2 then
    PSTATE.DIT = X[t, 64]&lt;24&gt;;
elsif PSTATE.EL == EL3 then
    PSTATE.DIT = X[t, 64]&lt;24&gt;;
                </p><h4 class="assembler">MSR DIT, #&lt;imm&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>op2</th></tr><tr><td>0b00</td><td>0b011</td><td>0b0100</td><td>0b010</td></tr></table></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
